1. Field of the Invention
The present invention relates to a memory system having a nonvolatile memory and a volatile memory, and an operating method of this memory system.
2. Description of the Related Art
Portable equipment such as a mobile phone, a digital camera, etc. has a volatile memory such as DRAM, etc. for temporarily holding data such as various kinds of parameters, etc. and a nonvolatile memory such as a flash memory, etc. for holding a program and data at a turning-off of a power supply. In general, in the flash memory of a NAND type, no data can be accessed at random, and access time is long. Therefore, when a program of MPU is stored in the flash memory of the NAND type, no MPU can smoothly execute the program. To solve this problem, a conventional memory system is formed of the flash memory and DRAM, and the program is transferred from the flash memory to DRAM at a turning-on of the power supply. MPU then reads the program from DRAM. For this case, there has been proposed a memory controller which executes data (program) transfer from the flash memory to DRAM without placing a load on MPU (e.g., Japanese Unexamined Patent Application Publication No. 2002-328836). This memory controller reads real data in the flash memory together with an error correction code, and corrects an error in the real data, and writes only the corrected real data to DRAM.
Further, there has been also proposed a technique for connecting data lines of the nonvolatile memory and the volatile memory to each other through a switch, and transferring data read out of one memory to another memory through the switch (e.g., Japanese Unexamined Patent Application Publication No. 63-181194). According to this technique, the nonvolatile memory does not have an area for storing the error correction code. Further, there has been proposed another technique for having an error correction circuit of the flash memory of the NAND type, a controller circuit and an interface circuit formed in the volatile memory (e.g.,Japanese Unexamined Patent Application Publication No. 2002-251884).
As mentioned above, for storing the program in the flash memory of the NAND type, it is necessary for MPU to read the program transferred from the flash memory to DRAM. In this case, MPU starts reading the program after the program is read from the flash memory, and all the error-corrected program is transferred to DRAM. Therefore, it takes much time from the start of the program transfer from the flash memory to DRAM to MPU's start of reading the program.
In particular, in a system in which the program is transferred from the flash memory to DRAM at a power-on, it takes a lot of time from the power-on to MPU's actual execution of the program. Specifically, it takes a long time for a user to operate a device after switching on the power supply of the device, deteriorating usability of the device.
On the other hand, when MPU starts reading the program before the transfer thereof to DRAM, there is a possibility that the execution of the program is stopped for a long time. Specifically, upon a read request for a program having not been transferred to DRAM, MPU must wait for a long time until this program is transferred to DRAM. The stoppage of the operation of MPU causes a problem in the system.